The present invention relates to a semiconductor device, specifically a power transistor in which a vertical type D-MOS transistor portion and a planar type MOS-IC portion for controlling the D-MOS transistor portion are integrated on a single semiconductor substrate.
Power MOS transistors are widely used as a switching element for different power loads. The demand for vertical type MOS transistors has especially been increasing because the vertical type MOS transistors have a low ON-resistance and are suitable for power switching.
FIG. 1 shows one example of a vertical type MOS transistor device, wherein the MOS transistor device comprises a n.sup.+ type semiconductor substrate 101 and n.sup.- type semiconductor region 103 formed on the substrate by an epitaxial growth, which jointly constitute a drain region of the vertical type MOS transistor device.
It should be noted that what is meant herein by the term "vertical type" transistor is a transistor having the drain region and the source region on the opposite sides thereof.
Formed in the n.sup.- type region 103 are a plurality of p type well regions 107, which contain a pair of n.sup.+ type source regions 109 and a p.sup.30 type well contact region 111 sandwiched by the source regions 109. They are formed by impurity diffusion using as a mask a polysilicon gate 113 for gate electrode.
On the transistor device, there is also formed a gate oxide film 115, a source electrode 117, an intermediate insulating layers 119 and a final protection film or layer 121.
In this vertical type MOS transistor, for example, with a drain voltage V.sub.d applied to the bottom side of the substrate 101 through an electrode 123 and with the n.sup.+ type source region 109 connected to the ground through a power load (not illustrated), the power supply to the polysilicon gate 113 is controlled to control the current flowing through the substrate 101, the n type region 103 and the n.sup.+ source region 109, thereby providing the so called "switching control", thus enabling the power load to be controlled.
In the vertical type MOS transistor, however, its switching function must be carried out by the control of the voltage applied to the gate electrodes 113 as described above. Accordingly, for practical use of the device, different peripheral circuits including the one for the power supply must be connected to the vertical type MOS transistor, although not shown in the drawing.
Forming the peripheral circuits as well as the vertical type MOS transistor on a single substrate would provide some merits such as realization of compact circuits, reduction in working processes, prevention of malfunction due to dispersions in the characteristics of parts, as compared with the case where the peripheral circuits are externally connected to the MOS transistor chip.
When the vertical type MOS transistors and the peripheral circuits thereof are formed on a single substrate of the MOS transistor, the peripheral circuit or circuits must be electrically isolated from the substrate 101 and the n.sup.- type region 103 which constitute a drain, that is a path for current of the vertical MOS transister. For this end, there has heretofore been proposed, for instance, in Japanese Pat. Publication of Unexamined Application No. 58-16432, a method for forming a p type region within part of the n.sup.- type region 103 and then connecting the p type region to the earth to form the peripheral circuit in the p type region.
In order to constitute the peripheral circuit with a MOS circuit according to the method as mentioned above, however, a complicated manufacturing process is required, such as forming the p type region in the n.sup.- type region 103 by diffusion technique, then forming the n.sup.+ type region in the p type region, and finally forming n-channel and p-channel MOS transistors respectively in the p type and n.sup.- type regions. In addition, the following problem occurs.
It is another object of the present invention to provide a vertical type D-MOS transistor and a planar type MOS-IC integrated on a single substrate by forming an epitaxial region on the substrate, forming a well region for the vertical type D-MOS transistor within part of the epitaxial region by diffusion throughout the epitaxial region in the direction to the substrate.
Namely, in order to reduce the ON-resistance of the vertical type MOS transistor, the n.sup.- type region 103 has to have a somewhat high impurity concentration, resulting in that the p type region formed in the n.sup.- type region 103 and the n.sup.+ type regions formed in the p type region for the peripheral circuit must also have a progressively higher impurity concentration. Consequently, the threshold voltage V.sub.T of the MOS transistor formed in either p-channel or n-channel type MOS transistor tends essentially to be high and it is no longer suitable for use as a peripheral circuit.